A chiplet design for the AMD Navi 31 GPU has six Memory Cache Dies and one Graphics Compute Die (MCDs). Each of the outer dies has two 32-bit memory controllers, along with a sizable L3 cache. While the primary graphics die uses a TSMC 5nm node, these less important memory and cache controllers were placed on a less expensive TSMC 6nm node.
The L0, L1, and L2 caches have not yet been confirmed by AMD, but the company has so far stated that the entire Navi 31 GPU contains 96MB of L3 Cache (also known as Infinity Cache). On the most recent slide, these are mentioned:
L0 – 3MB – 240% increase
L1 – 3MB – 300% increase
L2 – 6MB – 50% increase
L3 (Infinity Cache) – 96MB (32MB smaller than Navi 21)
This diagram displays the layout of the AMD Navi 31 six Shader Engines, each with eight dual compute units. By incorporating dual-issue SIMD into their design, AMD has doubled computation throughput but not core count. Due to this, even though there are 6144 stream processors, single-precision computing performance is now 61 TFLOPS.
The RDNA3 architecture will have a frequency of above 3 GHz, according to the slide. Even while the baseline design is only capable of 2.5 GHz boost, this may support rumours that the architecture can scale up to 3.0 GHz.
The AMD Radeon RX 7900 series is currently scheduled to debut on December 13. RDNA3 architecture specifics may or may not be subject to a different embargo, but it is clear that there are still further slides that could be released sooner.
